1. Field of Invention
The present invention relates to semiconductor memory and in particular to verification of sense and program operations for non-volatile memory.
2. Description of Related Art
The requirements for increase performance in low power systems has caused an increased demand for high speed and low power non-volatile semiconductor memory devices, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable read only memory (EEPROM), and flash EEPROM. To achieve a high performance non-volatile memory the memory cell needs to have high current capability as well as a low power and high performance read path. The non-volatile memory can be either a NOR type or a NAND type arrangement depending upon the connectivity between the cells and the bit lines. Because the cell current is higher in the NOR connected cell, the NOR connected cell is more suited for high performance than the NAND connected cell.
In U.S. Pat. No. 6,618,297 B1 (Manea) the establishment of boundary current levels is directed to providing more than two memory states for a non-volatile memory. The reference currents are defined by multiple pre-programmed reference memory cells. U.S. Pat. No. 6,044,019 (Cemea et al.) is directed to canceling inherent noise fluctuations by averaging the sensing of current from a reference cell over a predetermined period of time, thus increasing the accuracy of sensing. The increased sensing accuracy allows a higher resolution of the conduction states of a non-volatile memory cell and alloys the cell to store more than one bit of data. U.S. Pat. No. 5,712,815 (Bill et al.) is directed to an improved programming structure in a non-volatile memory array containing multiple bits per cell. The memory array contains a plurality of memory cells and a reference cell array, which contains a plurality of reference cells by which programming and verifying the multiple bits is achieved. In U.S. Pat. No. 5,124,945 (Schreck) an apparatus is directed to verifying the state of a plurality of electrically programmable memory cells.
Data is stored in a non-volatile memory by changing the threshold voltage of the individual cells. The memory cells have at least two states, programmed and erased. More states are available by creating additional programmed states in which there are additional threshold voltage levels used. In FIG. 1 is shown the distribution of threshold voltages for an erased state representing a logical “1” and for a programmed state representing a logical “0”. The erased state typically represents a logical “1” and the programmed state typically represents a logical “0”. From FIG. 1 it is seen that both the erased and programmed states are formed from a range of voltages. The separation between the programmed and erased states should be large enough to allow a sensing circuit to distinguish between the states.
Continuing to refer to FIG. 1, in conventional nonvolatile memories, a reference cell used for reading has a threshold voltage Vref1 10 that is located between the erased state and the programmed state. The reference voltage applied to the reference cell is used to establish a current that is compared to the memory cell being read in order to determine whether the value of the stored data in the memory cell is a logical “1” or a logical “0”. When the memory cell that is being read is in an erased state, the memory cell being read conducts more current than the reference cell because the memory cell being read has a lower threshold voltage. When the memory cell that is being read is in a programmed state, the memory cell being read conducts less current than the reference cell because the memory cell being read has a higher threshold voltage.
Referring to FIG. 2, an example of a conventional read circuit is shown. The memory cell 22 is located within a block of memory cells that is coupled to the read path circuitry, which includes the column decoder 25, the bit line bias circuit 26 and column load 27. The output of the read column 40 is coupled to the negative input of the sense amplifier 28. The reference cell 30, which connects 41 to the positive input to the sense amplifier 28, can be located within the memory or separately from the memory. The reference cell 30 is coupled to its own read path through a reference column decoder 31, a reference bias circuit 32 and a reference column load 33. When a memory cell is selected, the cell current creates a voltage drop at node 40 connected to the negative input to the sense amplifier. The voltage drop is a function of the selected memory cell current in which the higher the selected memory cell threshold voltage the lower the memory cell current. The sense amplifier then compares the voltage drop at node 41 caused by the current of the reference cell to the voltage drop at node 40 caused by the current of the memory cell being read.
A series of interleaved write and verify operations are performed in a conventional programming operation, an example of which is shown in FIG. 3. The gate voltage for each successive write pulse increases whereas the gate voltage during the verify operation remains constant throughout the programming operation. A regulated voltage greater than 10V is applied to the gate and a regulated voltage of 5V is coupled to the drain of the NOR memory cell being programmed to establish a channel-hot-electron (CHE) mechanism in the memory cell and to write a logical “0” into an erased cell having a threshold voltage representing a logical “1”. After a predetermined amount of time the write operation is stopped and a verify operation using the reference cell is performed to determine if the memory cell is under-programmed. The verify reference cell threshold of Vref2 11 (shown in FIG. 1) is set at the lower edge of the distribution of the program state. The applied gate voltage to the reference cell is set approximately to Vref2 11, or slightly above. If the memory cell is under-programmed, additional write and verify operations are performed until the threshold voltage of the memory cell reaches the programmed state.
In the non-volatile memories the use of multi-bits per cells is used to increase the number of programmed states. The reference cells used for read and program operations are precisely programmed during manufacture under a controlled environment. In U.S. Pat. No. 5,444,656 (Bauer et al.), a method to trim reference cells was introduced, especially for memories with multi bits per cell. FIG. 4 illustrates a schematic diagram of a conventional memory where additional reference cells are used to provide capability to read and program multi-bits per cell. A plurality of memory cells 22 are coupled to column decoders 25 and then to bit line bias circuits 26 and column load 27 similarly as shown in FIG. 2. A plurality of reference cells 30 are coupled to a plurality of reference column decoders 31 and then to a reference bias circuit 32 and the reference circuit load 33. The negative input to the sense amplifier is coupled to the column load 40, and the positive input of the sense amplifier is coupled to the reference circuit load 41. A controller 51 selects the reference decoder connected to the reference cell, which is to be programmed. The controller 51 also closes a switch 52, which allows an external voltage to be applied to the negative input of the sense amplifier, and at the same time a voltage is coupled to the gate of the reference cell that is to be programmed through an external pad or a DAC 53. The sense amplifier 28 compares the voltage applied through switch 52 to the threshold voltage of the reference cell 30 and adjusts the voltage applied to gates of the reference cells through the external pad or DAC 53. The method of establishing the reference cell threshold voltages is a slow process performed on every non-volatile memory chip. The circuitry involved in programming the reference cells, including the reference circuits, consume a large amount of power and silicon area.